1. Field of the Invention
This invention is related to a method of making a semiconductor device, more particularly, to a dielectric isolation type semiconductor device in which a plurality of semiconductor segments are integrated in one chip.
2. Description of the Related Art
Many kinds of structures for separating several semiconductor segments mounted on the same substrate in one semiconductor device are known, but recently, manufacturers have concentrated on the dielectric isolation type semiconductor device, due to its superior withstand voltage, capacity, processing speed, and leakage properties.
This structure for electrically isolating a plurality of semiconductor segments mounted on the same substrate is very important in the field of "intelligent" power devices, in which the plurality of semiconductor segments are mounted on the same substrate to form one chip, and accordingly, several proposals have been made with regard to the manufacture of such a semiconductor device.
For example, Japanese Unexamined Patent Publication 61-59853 discloses that such an isolation structure is produced by first preparing a semiconductor substrate having a silicon oxide film partially covering the surface thereof, and then connecting another semiconductor substrate to that surface to position the silicon oxide film inside of the stacked semiconductor layer, and thereafter, a plurality of oxide films, isolated from each other and extending vertically from the top surface of the substrate to the surface of the oxide film buried inside the substrate, are formed to isolate the portion surrounded by the oxide film buried inside the substrate and at least two of the vertical oxide films, from the other portion. This vertical oxide film is referred to hereinafter as the isolation region.
In this structure, however, the boundary face between the different substrates consists only of the oxide film, and therefore, the isolated portion can not be completely electrically isolated from the other portion, and accordingly, the characteristic of the semiconductor device formed in that portion will be affected by variations in the electric potential of the other substrate.
The article "Research and Development of SOI Technology Utilizing Oxygen Ion Implantation Improved by Completion of the High Current Ion Implanter" [NIKKEI MICRODEVICES, (Mar., 1987, pages 81 to 95)] shows that the formed isolated portion is surrounded by walls consisting of the silicon oxide films on a side portion thereof and a semiinsulating polycrystalline silicon layer as a bottom portion thereof.
But, in this structure, the semiinsulating polycrystalline silicon layer formed on the insulating film by utilizing the oxygen ion implantation method usually has a low electric conductivity, due to the presence of SiO.sub.2 in the layer, and accordingly, the semiconductor device formed in that portion has inferior properties.
The article, "Dielectric Separation Type Intelligent Power Switch" [EDD-86-61, pages 29 to 37,] shows one process of manufacturing the dielectric isolation type semiconductor device. This process will be explained sequentially hereunder with reference to FIGS. 8(a) to 8(f).
As shown in FIG. 8(a), the surface of the N type silicon substrate 100, is given a mirror-finish and then subjected to an ion implantation of a high concentration of N type impurities, to form an N.sup.+ type silicon layer 105, and then the main surface of this N.sup.+ type silicon substrate 105 is oxidized to form an oxide film 106.
A separate N type silicon substrate 101 containing a high concentration of N type impurities (i.e., N.sup.+ type silicon substrate) is then prepared, the surface thereof is oxidized to form an oxide film 107, and that surface then treated to give it a mirror-finish.
Thereafter, as shown in FIG. 8(b), each of the main surfaces of these N type silicon substrates 100 and 101 are connected to each other, in such a way that both oxide films are in indirect contact with each other, by a direct-connection method.
Next, as shown in FIG. 8(c), to form a lateral type power MOS transistor, etching is carried out on another main surface 108 of the predetermined region of the N type silicon substrate 100, opposite to the surface having the oxide film 106, to form a groove extending from the surface 108 to a portion inside the N.sup.+ type silicon substrate 101 beyond the oxide films 106, 107, whereby a portion of the silicon (Si) and a portion of the silicon oxide (SiO.sub.2) are removed.
This etching operation must be repeated three times, since a different etchant is used for each N type silicon substrate 100 and 101, respectively, based on the type of oxide film thereon.
Then, as shown in FIG. 8(d), an epitaxial layer 102 having a predetermined concentration of N type impurities therein is epitaxially grown, and thereafter, the surface thereof is smoothed and brought to a predetermined thickness by etching, or by rubbing and grinding, as shown in FIG. 8(e).
Then, as shown in FIG. 8(f), a predetermined portion of the N type silicon substrate 100 is etched by reactive ion etching (RIE) to form a groove extending from the surface thereof to the oxide film 106, and thereafter, a thermal oxide film 103 is formed on the inside surface of the groove by thermal oxidation, and finally, the groove is filled with polycrystalline silicon 104.
Accordingly, the semiconductor device thus produced has a region A consisting of the N.sup.+ type silicon substrate 101 and the epitaxial layer 102, and a region B surrounded by the thermal oxide film 103 and the polycrystalline silicon 104, and these regions A and B are electrically isolated from each other by the thermal oxide film 103, the polycrystalline silicon 104, and the oxide films 106 and 107 disposed between the substrates 100 and 101.
Therefore, when an electric power segment, for example, a power MOS transistor or the like using another main surface 109 of the semiconductor substrate 101 as one electrode is provided in the portion A, and a semiconductor segment, for example, a bipolar transistor, a CMOSFET or the like, for controlling the electric power segment is provided on the surface of the portion B, an "intelligent" type power device can be constructed.
Nevertheless, the known semiconductor device constructed as described above still has drawbacks such that the oxide films 106 and 107 formed between the N type silicon substrates 100 and 101 can not completely electrically isolate the substrates 100 and 101, and further, the characteristics of the semiconductor segment formed in the region B are adversely affected by variations of the electrical potential of the N type silicon substrate 101. This occurs because, for example, when the electric potential of the N type silicon substrate 101 is varied in accordance with the operational condition of the electric power device provided in the region A, or due to external noise, the threshold voltage of a segment such as a MOSFET or the like provided in the region B will be greatly changed due to the occurrence of a back channel in the segment, caused by this variation.
A further drawback arises in that, during the manufacture of the known semiconductor device as described above, when forming a vertical type semiconductor segment, for example, a power MOS transistor, especially in the region A, a part of the N type silicon substrates 100 and 101 and a part of the oxide films 106 and 107 must be removed, and thereafter, the growth of the epitaxial layer 102 and the grinding operation for smoothing the surface thereof, to form the semiconductor segment thereon, must be carried out. Consequently, the whole process becomes complex, and thus the manufacturing yield is lowered, and accordingly, the production costs are increased.